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High-Speed Microcontroller User’s
Guide: Network Microcontroller
Supplement
132
24-Bit Contiguous Addressing Mode
When the AM1 bit is set, the DS80C400 operates in its 24-bit contiguous addressing mode. This addressing mode supports a full 24-
bit program counter and eight modified instructions that operate over the full 24-bit address range. All modified branching instructions
automatically store and restore the entire contents of the 24-bit program counter. The 24-bit DPTR, DPTR1, DPTR2, and DPTR3 regis-
ters function identically to the program counter to allow access to the full 24-bit data memory range.
All the DS80C400 instruction op codes retain binary compatibility to the 8051. Modified instructions are different only with respect to
their cycle/byte/operand count and operate within a contiguous 24-bit address field. Note that all instructions utilizing the DPTR regis-
ter now make use of a full 24-bit register (DPTR = DPXn + DPHn + DPLn where n = 0, 1, 2, or 3). This mode of operation requires soft-
ware tools (assembler or compiler) specifically designed to accept the modified length of the new instructions.
In addition, the 24-bit contiguous mode utilizes the MXAX register to supply the upper 8 bits of the 24-bit MOVX address during regis-
ter-indirect MOVX instructions such as MOVX @Ri, A or MOVX A, @Ri. In this mode, the complete MOVX addr
ess is formed by con-
catenating MXAX, P2, and R1 or R0. The DPTR-related MOVX instructions do not utilize the P2 and MXAX register.
The instructions modified to operate in the 24-bit contiguous address mode are summarized in the following table.
INSTRUCTION CODE
MNEMONIC
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
HEX
BYTE
CYCLE
EXPLANATION
ACALL addr 19
a
18
a
15
a
7
a
17
a
14
a
6
a
16
a
13
a
5
1
a
12
a
4
0
a
11
a
3
0
a
10
a
2
0
a
9
a
1
1
a
8
a
0
Byte 1
Byte 2
Byte 3
3 5 (PC) = (PC) + 3
(SP) = (SP) + 1
((SP)) = (PC
7:0
)
(SP) = (SP) + 1
((SP)) = (PC
15:8
)
(SP) = (SP) + 1
((SP)) =
(PC
23:16
)
(PC
18:0
) =
addr19
AJMP addr 19
a
18
a
15
a
7
a
17
a
14
a
6
a
16
a
13
a
5
0
a
12
a
8
0
a
11
a
3
0
a
10
a
2
0
a
9
a
1
1
a
8
a
0
Byte 1
Byte 2
Byte 3
3 5 (PC) = (PC) + 3
(PC
18:0
) =
addr19
LCALL addr24 0
a
23
a
15
a
7
0
a
22
a
14
a
6
0
a
21
a
13
a
5
1
a
20
a
12
a
4
0
a
19
a
11
a
3
0
a
18
a
10
a
2
1
a
17
a
9
a
1
0
a
16
a
8
a
0
12
Byte 2
Byte 3
Byte 4
4 6 (PC) = (PC) + 4
(SP) = (SP) + 1
((SP)) = (PC
7:0
)
(SP) = (SP) + 1
((SP)) = (PC
15:8
)
(SP) = (SP) + 1
((SP)) =
(PC
23:16
)
(PC
23:0
) =
addr24
LJMP addr24 0
a
23
a
15
a
7
0
a
22
a
14
a
6
0
a
21
a
13
a
5
0
a
20
a
12
a
4
0
a
19
a
11
a
3
0
a
18
a
10
a
2
1
a
17
a
9
a
1
0
a
16
a
8
a
0
02
Byte 2
Byte 3
Byte 4
4 5 (PC
23:0
) =
addr24
MOV DPTR,
#data24
1
d
23
d
15
d
7
0
d
22
d
14
d
6
0
d
21
d
13
d
5
1
d
20
d
12
d
4
0
d
19
d
11
d
3
0
d
18
d
10
d
2
0
d
17
d
9
d
1
0
d
16
d
8
d
0
90
Byte 2
Byte 3
Byte 4
4 3 (DPX) =
#data23:9
(DPH) =
#data15:8
(DPL) = #data7:0
RET 00100010 22 1 5(PC
23:16
) =
((SP))
(SP) = (SP) - 1
(PC
15:8
) = ((SP))
(SP) = (SP) - 1
(PC
7:0
) = ((SP))
(SP) = (SP) - 1
RETI 0 0 1 1 0 0 1 0 32 1 5 (PC
23:16
) =
((SP))
(SP) = (SP) - 1
(PC
15:8
) = ((SP))
(SP) = (SP) - 1
(PC
7:0
) = ((SP))
(SP) = (SP) - 1
Maxim Integrated
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