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Secure Microcontroller User’s Guide
182 of 187
MNEMONIC
INSTRUCTION CODE
HEX BYTE CYCLE EXPLANATION
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
ARITHMETIC OPER.
DA A
1 1 0 1 0 1 0 0 D4 1 1
Contents of Accumulator
are BCD,
IF [[(A
3-0
) > 9] OR
[(AC) = 1]] THEN
(A
3-0
) = (A
3-0
) + 6
AND
IF [[(A
7-4
) > 9] OR
[(C) = 1]] THEN
(A
7-4
) = (A
7-4
) + 6
LOGICAL OPERATION
ANL A, Rn
0
1
0
1
1
n
2
n
1
n
0
58–5F
1
1
(A) = (A) AND (Rn)
ANL A, direct
0
a
7
1
a
6
0
a
5
1
a
4
0
a
3
1
a
2
0
a
1
i
a
0
55
Byte 2
2 1 (A) = (A) AND (direct)
ANL A, @Ri
0
1
0
1
0
1
1
i
56–57
1
1
(A) = (A) AND ((Ri))
ANL A, #data
0
d
7
1
d
6
0
d
5
1
d
4
0
d
3
1
d
2
0
d
1
0
d
0
54
Byte 2
2 1 (A) = (A) AND #data
ANL direct, A
0
a
7
1
a
6
0
a
5
1
a
4
0
a
3
0
a
2
1
a
1
0
a
0
52
Byte 2
2 1
(direct) =
(direct) AND A
ANL direct,
#data
0
a
7
d
7
1
a
6
d
6
0
a
5
d
5
1
a
4
d
4
0
a
3
d
3
0
a
2
d
2
1
a
1
d
1
1
a
0
d
0
53
Byte 2
Byte 3
3 2
(direct) =
(direct) AND #data
ORL A, Rn
0
1
0
0
1
n
2
n
1
n
0
48–4F
1
1
(A) = (A) OR (Rn)
ORL A, direct
0
a
7
1
a
6
0
a
5
0
a
4
0
a
3
1
a
2
1
a
1
I
a
0
45
Byte 2
2 1
(A) =
(A) OR (direct)
ORL A, @Ri
0
1
0
0
0
1
1
i
46–47
1
1
(A) = (A) OR ((Ri))
ORL A, #data
0
d
7
1
d
6
0
d
5
0
d
4
0
d
3
1
d
2
0
d
1
0
d
0
44
Byte 2
2 1 (A) = (A) OR #data
ORL direct, A 0 1 0 0 0 0 1 0
42
Byte 2
2 1
(direct) =
(direct) OR (A)
ORL direct,
#data
0
a
7
d
7
1
a
6
d
6
0
a
5
d
5
0
a
4
d
4
0
a
3
d
3
0
a
2
d
2
1
a
1
d
1
1
a
0
d
0
43
Byte 2
Byte 3
3 2
(direct) =
(direct) OR #data
XRL A, Rn
0
1
1
0
1
n
2
n
1
n
0
68–6F
1
1
(A) = (A) XOR (Rn)
XRL A, direct
0
a
7
1
a
6
1
a
5
0
a
4
0
a
3
1
a
2
0
a
1
1
a
0
65
Byte 2
2 1
(A) =
(A) XOR (direct)
XRL A, @ Ri
0
1
1
0
0
1
1
i
66–67
1
1
(A) = (A) XOR ((Ri))
XRL A, #data 0 1 1 0 0 1 0 0
64
Byte 2
2 1
(direct) =
(A) XOR #data
XRL direct, A 0 1 1 0 0 0 1 0
62
Byte 2
2 1
(direct) =
(direct) XOR (A)
XRL direct,
#data
0
a
7
d
7
1
a
6
d
6
1
a
5
d
5
0
a
4
d
4
0
a
3
d
3
0
a
2
d
2
1
a
1
d
1
1
a
0
d
0
63
Byte 2
Byte 3
3 2
(direct) =
(direct) XOR #data
CLR A
1
1
1
0
0
1
0
0
E4
1
1
(A) = 0
CPL A
1
1
1
1
0
1
0
0
F4
1
1
(A) = (A)
- Rev 1/14 1
- TABLE OF CONTENTS 2
- 4 of 187 4
- LIST OF FIGURES 5
- LIST OF TABLES 6
- 1. INTRODUCTION 7
- 1.2 Software Security 7
- Separate Address/Data Bus 8
- Large Nonvolatile Memory 8
- In-System Loading 8
- High-Reliability Operation 8
- 1.3 Product Description 9
- 2. SELECTOR GUIDE 12
- 13 of 187 13
- Scratchpad Registers 14
- Serial I/O 14
- Programmable Timers 14
- 15 of 187 15
- Parallel I/O 16
- Program/Data RAM Interface 16
- High-Reliability Circuitry 16
- Software Encryption Logic 16
- Security Lock Logic 16
- Vector RAM 17
- Timed-Access Logic 17
- Watchdog Timer 17
- Resident Loader ROM 17
- 4. PROGRAMMER’S GUIDE 18
- 4.1.1 Internal Registers 19
- 21 of 187 21
- DS5000 SERIES MCON REGISTER 24
- Partition Table 25
- 29 of 187 29
- 30 of 187 30
- 32 of 187 32
- Figure 4-9. DS5000 SFR Map 34
- 35 of 187 35
- PCON, 087H 36
- Power Control Register 36
- Timer Control Register 37
- TCON, 088H 37
- Timer Mode Register 38
- TMOD, 089H 38
- Serial Control Register 39
- SCON, 098H 39
- Interrupt Enable Register 40
- IE, 0A8H 40
- Interrupt Priority Register 41
- IP, 0B8H 41
- DS5001 CRC Register 42
- CRC, 0C1H 42
- MCON, 0C6H 42
- 43 of 187 43
- PAA 43
- DS5001/DS5002 MCON Register 44
- Program Status Word Register 45
- PSW, 0D0H 45
- RPCTL, 0D8H 46
- RPS, 0DAH 47
- 4.9 Instruction Set 48
- 4.10 Addressing Modes 48
- 49 of 187 49
- 4.11 Program Status Flags 50
- 5. MEMORY INTERCONNECT 51
- DS5002FP 54
- 6. LITHIUM/BATTERY BACKUP 58
- 6.1 Data Retention 58
- Battery-Backed Circuits 58
- Battery-Attach Procedure 59
- Battery Lifetime 60
- Using Lithium Cells 61
- Freshness Seal 61
- 7. POWER MANAGEMENT 62
- 7.1 Idle Mode 62
- 63 of 187 63
- 7.2 Stop Mode 64
- 7.4 Power-Fail Interrupt 64
- 7.5 Total Power Failure 65
- 7.6 Partial Power Failures 66
- 8. SOFTWARE CONTROL 68
- 8.1 Timed Access 68
- Figure 8-1. Timed Access 69
- 8.2 Watchdog Timer 70
- 8.3 CRC Memory Verification 71
- 72 of 187 72
- Figure 8-2. CRC Code Example 73
- 9. FIRMWARE SECURITY 74
- Security Overview 74
- 9.1 Security Lock 74
- 9.2 RAM Memory 75
- 9.3 Encrypted Memory 76
- 77 of 187 77
- 9.4 Encryption Algorithm 78
- 9.5 Encryption Key 78
- 9.7 Dummy Bus Access 79
- 9.8 On-Chip Vector RAM 79
- 9.9 Self-Destruct Input 80
- 81 of 187 81
- Avoid Clear Text 82
- Avoid CRC or Checksum 83
- Use Random Values 83
- Change Code 83
- External Circuits 84
- Tamper Protection 84
- 10. RESET CONDITIONS 85
- 10.1 Reset Sources 85
- Reset Status Bits 85
- Table 10-A. SFR Reset States 86
- 10.1.1 Power-On Reset 87
- 10.1.2 No-V 88
- Power-On Reset 88
- 10.1.3 External Reset 88
- 10.1.4 Watchdog Timer Reset 88
- 10.2 Memory Map 89
- 10.3 Interrupts 90
- 10.4 Timers 90
- 91 of 187 91
- 11. INTERRUPTS 92
- 11.1 Interrupt Sources 92
- 11.2 External Interrupts 93
- 11.3 Timer Interrupts 93
- 11.4 Serial Port Interrupts 93
- 11.6 Simulated Interrupts 94
- 11.7 Interrupt Priorities 96
- 11.8 Interrupt Acknowledge 97
- 12. PARALLEL I/O 99
- 12.1 Output Functions 102
- 12.2 Input Function 103
- 12.5 RPC Interrupts 106
- 12.6 RPC Protocol 107
- 12.7 DMA Operation 107
- 108 of 187 108
- 13. PROGRAMMABLE TIMERS 109
- 13.1 Functional Description 109
- 110 of 187 110
- 13.2 Mode 0 111
- 13.3 Mode 1 111
- 13.4 Mode 2 112
- 13.5 Mode 3 114
- 14. SERIAL I/O 115
- 14.1 Function Description 115
- Serial Port Control Register 117
- 14.2 Baud Rate Generation 118
- 119 of 187 119
- 14.4 Asynchronous Operation 120
- 121 of 187 121
- 122 of 187 122
- 123 of 187 123
- 124 of 187 124
- Mode 2 and 3 125
- 126 of 187 126
- 127 of 187 127
- 128 of 187 128
- 15. CPU TIMING 130
- 15.1 Oscillator 130
- 15.2 Instruction Timing 131
- 132 of 187 132
- 136 of 187 136
- 16. PROGRAM LOADING 137
- 138 of 187 138
- 16.4 Exiting the Loader 139
- 142 of 187 142
- 16.8 Command Line Interface 143
- 16.9 Command Line Syntax 143
- Important Application Note 144
- 16.10 Command Summaries 145
- 146 of 187 146
- 147 of 187 147
- 16.11 Error Messages 148
- 16.12 Intel Hex File Format 149
- 152 of 187 152
- 153 of 187 153
- 154 of 187 154
- 17. REAL-TIME CLOCK (RTC) 155
- 17.1 DS5000T/DS2250T RTC 155
- 156 of 187 156
- 17.3 Registers 160
- 17.4 Special Bits 160
- 17.5 DS2251T/DS2252T RTC 162
- 17.6 Memory Map 163
- 165 of 187 165
- 166 of 187 166
- 168 of 187 168
- 169 of 187 169
- 170 of 187 170
- 171 of 187 171
- 172 of 187 172
- 173 of 187 173
- 174 of 187 174
- 175 of 187 175
- 18. TROUBLESHOOTING 176
- 177 of 187 177
- 178 of 187 178
- 18.7 Do’s and Don’ts 179
- 180 of 187 180
- 19. INSTRUCTION SET DETAILS 181
- MNEMONIC 183
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