Maxim-integrated DS4830A Optical Microcontroller Manuale Utente Pagina 70
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DS4830A User’s Guide
70
8.2 – Sample and Hold Register Descriptions
The sample and hold has two SFRs. These are Sample and Hold Control Register (SHCN) and Sample and Hold
Internal Trigger Enable register (SENR). The SHCN register controls both sample and holds. The SENR controls
the internal sample pulse for both sample and holds. The sample and hold SFRs are located in module 4.
8.2.1 – Sample and Hold Control Register (SHCN)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
SSC[3:0]
FAST_MODE
PIN_DIS1
PIN_DIS0
SH_DUAL
-
SH1_ALIGN
SHDAI1_EN
SMP_HLD1
CLK_SEL
SH0_ALIGN
SHDAI0_EN
SMP_HLD0
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Access
rw
rw
rw
rw
rw
rw
rw
rw
r
rw
rw
rw
rw
rw
rw
rw
BIT
NAME
DESCRIPTION
15:12
SSC[3:0]
STOP Sample Control. These bits control the end of the sample and hold sampling
relative to the SHEN0 and SHEN1 pulse.
CLK_SEL = 0
SSC[3:0]
STOP Sampling
0000
Falling Edge of SHEN0/SHEN1
0001
Reserved
0010
Reserved
0011
Reserved
0100
300ns after rising edge of SHEN0/SHEN1
0101
350ns after rising edge of SHEN0/SHEN1
0110
450ns after rising edge of SHEN0/SHEN1
0111
550ns after rising edge of SHEN0/SHEN1
1000
750ns after rising edge of SHEN0/SHEN1
1001
1us after rising edge of SHEN0/SHEN1
1010
1.5us after rising edge of SHEN0/SHEN1
1011
1.75us after rising edge of SHEN0/SHEN1
1100
2us after rising edge of SHEN0/SHEN1
1101
2.5us after rising edge of SHEN0/SHEN1
1110
4us after rising edge of SHEN0/SHEN1
1111
5us after rising edge of SHEN0/SHEN1
CLK_SEL = 1
SSC[3:0]
STOP Sampling
0000
Falling Edge of SHEN0/SHEN1
0001
21 ext-clock after rising edge of SHEN0/SHEN1
0010
22 ext-clock after rising edge of SHEN0/SHEN1
0011
23 ext-clock after rising edge of SHEN0/SHEN1
0100
24 ext-clock after rising edge of SHEN0/SHEN1
0101
25 ext-clock after rising edge of SHEN0/SHEN1
0110
26 ext-clock after rising edge of SHEN0/SHEN1
0111
27 ext-clock after rising edge of SHEN0/SHEN1
1000
28 ext-clock after rising edge of SHEN0/SHEN1
1001
29 ext-clock after rising edge of SHEN0/SHEN1
1010
30 ext-clock after rising edge of SHEN0/SHEN1
1011
31 ext-clock after rising edge of SHEN0/SHEN1
1100
32 ext-clock after rising edge of SHEN0/SHEN1
1101
33 ext-clock after rising edge of SHEN0/SHEN1
1110
34 ext-clock after rising edge of SHEN0/SHEN1
1111
35 ext-clock after rising edge of SHEN0/SHEN1
Note: A minimum sample time of 300nSec must be used when external clock is
used to guarantee accurate results.
11
FAST_MODE
Fast Mode Enable. Setting this bit to ‘1’ enables the fast operation for Sample and Hold
0. In this mode, Sample and Hold 0 is guaranteed to get a conversion slot in the ADC
conversion sequence every 125µs and the user can issue sample pulses at an interval
of 125µs. During fast mode, the sample and hold conversion priority is increased over
voltage channels in the sequence and the voltage conversions will be delayed. When
- DS4830A 1
- Optical Microcontroller 1
- User’s Guide 1
- Contents 2
- DS4830A User’s Guide 10
- SECTION 1 – OVERVIEW 11
- SECTION 2 – ARCHITECTURE 13
- 2.2 – Register Space 14
- 2.3 – Memory Types 15
- 2.5 – Data Alignment 22
- 2.6 – Reset Conditions 22
- 2.7 – Clock Generation 24
- INT_TRIG1 38
- INT_ALIGN 38
- BOOT_DIS 38
- SECTION 5 – INTERRUPTS 40
- 5.1 – Servicing Interrupts 41
- 6.1 – Detailed Description 45
- 6.3 – DAC Code Examples 47
- 7.1 – Detailed Description 48
- 7.3 – ADC Code Examples 63
- SECTION 8 – SAMPLE AND HOLD 65
- INT_TRIG_EN1 72
- INT_TRIG_EN0 72
- 9.1 – Detailed Description 73
- SECTION 10 – I 81
- 10.2 – I 90
- SECTION 11 – I 94
- C-COMPATIBLE SLAVE INTERFACE 94
- 11.1 – Detailed Description 95
- Detect START 96
- I2CSRI=1 96
- I2CBUS=1 96
- I2CBUSY=1 96
- 100 100
- 101 101
- 102 102
- 104 104
- 105 105
- 106 106
- 107 107
- 108 108
- 109 109
- 110 110
- SPI Slave 111
- 112 112
- 113 113
- 12.2 – SPI System Errors 113
- 114 114
- 115 115
- 116 116
- 117 117
- 118 118
- 119 119
- 120 120
- SECTION 13 – 3-WIRE 121
- 122 122
- 123 123
- Using PWMCN and 124
- 125 125
- 128 128
- 129 129
- 130 130
- 131 131
- 132 132
- 133 133
- 134 134
- FrequencyClockPWM 135
- FrequencyFrame 135
- 136 136
- 137 137
- 138 138
- 15.1 – Overview 138
- 140 140
- 141 141
- 142 142
- 143 143
- 16.1 – Detailed Description 143
- 144 144
- 145 145
- 146 146
- 147 147
- MULTIPLIER 148
- 149 149
- 150 150
- 151 151
- 152 152
- 153 153
- 154 154
- 155 155
- 156 156
- 19.1 - Overview 156
- 157 157
- 158 158
- 159 159
- 160 160
- 20.1 – TAP Controller 160
- 161 161
- 20.2 – TAP State Control 161
- 162 162
- 20.3 – Communication via TAP 162
- 163 163
- 164 164
- 165 165
- 166 166
- 167 167
- 168 168
- 169 169
- 170 170
- 21.2 – Debug Mode 170
- 171 171
- 172 172
- 173 173
- 174 174
- 175 175
- 176 176
- 177 177
- 178 178
- 179 179
- 22.1 – Detailed Description 179
- 180 180
- 181 181
- 182 182
- 22.2 – Bootloader Operation 182
- 183 183
- 184 184
- 22.3 – Bootloader Commands 184
- 185 185
- 186 186
- 187 187
- 188 188
- 189 189
- SECTION 23 – PROGRAMMING 190
- 191 191
- 192 192
- 193 193
- 194 194
- 195 195
- 196 196
- 197 197
- – Controlling Program Flow 197
- 198 198
- 199 199
- – Handling Interrupts 199
- 200 200
- – Accessing the Stack 200
- 201 201
- – Accessing Data Memory 201
- 202 202
- SECTION 24 – INSTRUCTION SET 203
- 204 204
- 205 205
- 206 206
- 207 207
- 208 208
- 209 209
- 210 210
- 211 211
- 212 212
- 213 213
- 214 214
- 215 215
- 216 216
- 217 217
- 218 218
- 219 219
- 220 220
- 221 221
- 222 222
- 223 223
- 224 224
- 225 225
- 226 226
- 227 227
- 228 228
- 229 229
- 230 230
- SECTION 25 – UTILITY ROM 231
- 232 232
- 233 233
- 234 234
- 235 235
- 236 236
- 237 237
- 25.4 Special Functions 237
- 238 238
- 25.5 – Utility ROM Examples 238
- SECTION 26 – MISCELLANEOUS 239
- 240 240
- 26.5 – Device Number and I 240
- C Bootloader Address Disable 240
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